`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    02:54:02 02/28/2014 
// Design Name: 
// Module Name:    clock_div_25MHz 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clock_div_25MHz(pixel_clk, clk);
	input clk;
	output reg pixel_clk;
	reg [1:0] div = 0;
	
	always @ (posedge clk) begin
		div <= div + 1'b1;
		pixel_clk <= div[1];
	end

endmodule